Wafer-level-chip-scale packaging (WLCSP) is a type of package for integrated circuits (ICs) or Micro-Electromechanical System (MEMS), having an area that no greater than 120% of the area of the chip or die it contains, and is generally surface mountable. Face-to-Face (F2F) packaging is a type of WLCSP in which multiple dies or chips of a microelectronic system are vertically stacked and electrically coupled within a single package reducing a size or footprint of the package. F2F packages utilize copper (Cu) pillar or bumps and redistribution layers (RDL) to interconnect bond pads formed on exposed facing surfaces of the chips. Cu pillars allow a finer pitch, reduce the probability of interconnect bridging, and decrease the capacitance load for the circuits, as compared to flip-chip technology using solder bumps, thereby allowing the microelectronic system to operate at higher frequencies. Multi-chip-modules (MCM) are particular advantageous for integrally packaging chips including circuits or components fabricated using incompatible technologies. For example, F2F packaging can be used where a first substrate or chip including logic circuits or a processor, typically fabricated using complementary metal-oxide-semiconductor (CMOS) technology, is electrically coupled to and integrally packaged with a second chip including an IC, such as a memory, or a MEMS fabricated using processes incompatible with CMOS technology.
Problems with conventional F2F packaging utilizing Cu pillar and/or RDLs include diffusion of hydrogen through conductive and non-conductive layers surrounding a component in the IC or MEMS including a material susceptible to degradation by hydrogen. For example, a ferroelectric random access memory (F-RAM) including a ferroelectric capacitor with a lead zirconate titanate (PZT) ferroelectric layer or a MEMS with a piezoelectric layer including PZT. It has been observed that when PZT is exposed to hydrogen, particular at elevated temperatures, the electrical properties of a PZT layer are severely degraded. Generally, there are two ways in which hydrogen is introduced to F2F packaged components. The first is during standard processing techniques used to form the Cu pillars and RDL, or other interconnects which typically require hydrogen species at elevated process temperatures. The second is from hydrogen generated within the chip itself. For example, water adsorbed within permeable layer of the chip structure can react with metals causing dissociation of the water releasing hydrogen.
Thus, there is a need for a F2F package and packaging method that minimizes hydrogen penetration into ICs or MEMS including a material susceptible to degradation by hydrogen generated during the packaging and interconnect forming processes. It is further desirable that structure of the F2F package minimizes penetration into ICs or MEMS of environmental hydrogen external to the chip itself.